Node Architecture Overview

Document Navigation by Audience

• Node software engineers: Sections 4, 5, 7, 9, 10, 11, 12, 14, 15
• RF and firmware engineers: Sections 3, 4.3, 7.5, 8, 12, 13, 14
• Platform and integration engineers: Sections 6, 7, 9, 10, 11, 16
• Program and operations stakeholders: Sections 1, 2, 10, 13, 16

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1. Purpose

This document provides the implementation-level specification for a single antenna node in the rocket telemetry ground station. It covers the internal software processes, inter-process communication, network ports, configuration protocols, and data pipelines required to operate a phased-array or motorized antenna with SDR hardware.

Target audience: firmware engineers, systems integrators, RF hardware technicians, and central-server backend developers who need to understand node internals.

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2. Node Runtime Overview

An antenna node is a single-board computer (SBC) or embedded system running:

• FastAPI control server (Python, HTTP)
• GNU Radio or C++ DSP pipeline (high-rate IQ processing)
• SoapySDR hardware driver abstraction (RF transceiver control)
• Antenna control daemon (phased-array weights, motor commands, or fixed stubs)
• Telemetry router (frame extraction, payload demultiplexing, event streaming)

These five software subsystems run independently and communicate via Inter-Process Communication (IPC) buses, file descriptors, and shared memory.

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Next: Read Node-Hardware-Interface to understand the RF, FPGA, and antenna components, or jump to your role above.